Dr. Sudhir Madan
Dr. Sudhir Madan – Specialist in Memory Bit Cell / Array Core Design / Fabrication
Since 1986 Dr. Sudhir Madan has experience in process, fabrication, and design of SRAM, DRAM and FRAM (Ferro-electric) memories. His areas of expertise include memory bit cell definition and array core designs, including both architecture and layout, sense-amplifier design, memory bit line noise coupling mitigation, data path design, design using low power and low leakage techniques, logic and array power domain partitioning for power reduction, redundancy, and critical path design simulations. A Distinguished Member of the Technical Staff at Texas Instruments, he established the Center for Excellence in SRAM cells and developed the industry’s smallest embedded bit cells for 250nm, 180nm and 130nm technology nodes. Dr. Madan is credited with 46 patents and 22 published papers.
His novel SRAM cell architecture patent (US 7,087,493) and array leakage patent (US 6,768,144) are used throughout the industry at 130nm, 90nm, 65nm, 45nm and 28nm and smaller nodes.